{"api_version":"1","generated_at":"2026-04-21T10:51:19+00:00","cve":"CVE-2026-29642","urls":{"html":"https://cve.report/CVE-2026-29642","api":"https://cve.report/api/cve/CVE-2026-29642.json","docs":"https://cve.report/api","cve_org":"https://www.cve.org/CVERecord?id=CVE-2026-29642","nvd":"https://nvd.nist.gov/vuln/detail/CVE-2026-29642"},"summary":{"title":"CVE-2026-29642","description":"A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as \"writes preserve values, reads ignore values,\" i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.","state":"PUBLISHED","assigner":"mitre","published_at":"2026-04-20 21:16:19","updated_at":"2026-04-20 21:16:19"},"problem_types":["n/a"],"metrics":[],"references":[{"url":"https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63","name":"https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://github.com/OpenXiangShan/XiangShan/issues/3934","name":"https://github.com/OpenXiangShan/XiangShan/issues/3934","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://docs.riscv.org/reference/isa/priv/machine.html","name":"https://docs.riscv.org/reference/isa/priv/machine.html","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html","name":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://www.cve.org/CVERecord?id=CVE-2026-29642","name":"CVE Program record","refsource":"CVE.ORG","tags":["canonical"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2026-29642","name":"NVD vulnerability detail","refsource":"NVD","tags":["canonical","analysis"]}],"affected":[{"source":"CNA","vendor":"n/a","product":"n/a","version":"affected n/a","platforms":[]}],"timeline":[],"solutions":[],"workarounds":[],"exploits":[],"credits":[],"nvd_cpes":[],"vendor_comments":[],"enrichments":{"kev":null,"epss":null,"legacy_qids":[]},"source_records":{"cve_program":{"containers":{"cna":{"affected":[{"product":"n/a","vendor":"n/a","versions":[{"status":"affected","version":"n/a"}]}],"descriptions":[{"lang":"en","value":"A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as \"writes preserve values, reads ignore values,\" i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields."}],"problemTypes":[{"descriptions":[{"description":"n/a","lang":"en","type":"text"}]}],"providerMetadata":{"dateUpdated":"2026-04-20T20:30:19.577Z","orgId":"8254265b-2729-46b6-b9e3-3dfca2d5bfca","shortName":"mitre"},"references":[{"url":"https://github.com/OpenXiangShan/XiangShan/issues/3934"},{"url":"https://github.com/OpenXiangShan/XiangShan/commit/5e3dd63"},{"url":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html"},{"url":"https://docs.riscv.org/reference/isa/priv/machine.html"}]}},"cveMetadata":{"assignerOrgId":"8254265b-2729-46b6-b9e3-3dfca2d5bfca","assignerShortName":"mitre","cveId":"CVE-2026-29642","datePublished":"2026-04-20T00:00:00.000Z","dateReserved":"2026-03-04T00:00:00.000Z","dateUpdated":"2026-04-20T20:30:19.577Z","state":"PUBLISHED"},"dataType":"CVE_RECORD","dataVersion":"5.2"},"nvd":{"publishedDate":"2026-04-20 21:16:19","lastModifiedDate":"2026-04-20 21:16:19","problem_types":["n/a"],"metrics":[],"configurations":[]},"legacy_mitre":{"record":{"CveYear":"2026","CveId":"29642","Ordinal":"1","Title":"CVE-2026-29642","CVE":"CVE-2026-29642","Year":"2026"},"notes":[{"CveYear":"2026","CveId":"29642","Ordinal":"1","NoteData":"A local attacker who can execute privileged CSR operations (or can induce firmware to do so) performs carefully crafted reads/writes to menvcfg (e.g., csrrs in M-mode). On affected XiangShan versions (commit aecf601e803bfd2371667a3fb60bfcd83c333027, 2024-11-19), these menvcfg accesses can unexpectedly set WPRI (reserved) bits in the status view (xstatus) to 1. RISC-V defines WPRI fields as \"writes preserve values, reads ignore values,\" i.e., they must not be modified by software manipulating other fields, and menvcfg itself contains multiple WPRI fields.","Type":"Description","Title":"CVE-2026-29642"}]}}}