{"api_version":"1","generated_at":"2026-04-21T10:52:34+00:00","cve":"CVE-2026-29643","urls":{"html":"https://cve.report/CVE-2026-29643","api":"https://cve.report/api/cve/CVE-2026-29643.json","docs":"https://cve.report/api","cve_org":"https://www.cve.org/CVERecord?id=CVE-2026-29643","nvd":"https://nvd.nist.gov/vuln/detail/CVE-2026-29643"},"summary":{"title":"CVE-2026-29643","description":"XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.","state":"PUBLISHED","assigner":"mitre","published_at":"2026-04-20 22:16:23","updated_at":"2026-04-20 22:16:23"},"problem_types":["n/a"],"metrics":[],"references":[{"url":"https://github.com/OpenXiangShan/XiangShan/pull/3966","name":"https://github.com/OpenXiangShan/XiangShan/pull/3966","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://docs.riscv.org/reference/isa/priv/machine.html","name":"https://docs.riscv.org/reference/isa/priv/machine.html","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html","name":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://github.com/OpenXiangShan/XiangShan/issues/3959","name":"https://github.com/OpenXiangShan/XiangShan/issues/3959","refsource":"cve@mitre.org","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://www.cve.org/CVERecord?id=CVE-2026-29643","name":"CVE Program record","refsource":"CVE.ORG","tags":["canonical"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2026-29643","name":"NVD vulnerability detail","refsource":"NVD","tags":["canonical","analysis"]}],"affected":[{"source":"CNA","vendor":"n/a","product":"n/a","version":"affected n/a","platforms":[]}],"timeline":[],"solutions":[],"workarounds":[],"exploits":[],"credits":[],"nvd_cpes":[],"vendor_comments":[],"enrichments":{"kev":null,"epss":null,"legacy_qids":[]},"source_records":{"cve_program":{"containers":{"cna":{"affected":[{"product":"n/a","vendor":"n/a","versions":[{"status":"affected","version":"n/a"}]}],"descriptions":[{"lang":"en","value":"XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state."}],"problemTypes":[{"descriptions":[{"description":"n/a","lang":"en","type":"text"}]}],"providerMetadata":{"dateUpdated":"2026-04-20T21:18:39.405Z","orgId":"8254265b-2729-46b6-b9e3-3dfca2d5bfca","shortName":"mitre"},"references":[{"url":"https://github.com/OpenXiangShan/XiangShan/issues/3959"},{"url":"https://github.com/OpenXiangShan/XiangShan/pull/3966"},{"url":"https://docs.riscv.org/reference/isa/priv/priv-csrs.html"},{"url":"https://docs.riscv.org/reference/isa/priv/machine.html"}]}},"cveMetadata":{"assignerOrgId":"8254265b-2729-46b6-b9e3-3dfca2d5bfca","assignerShortName":"mitre","cveId":"CVE-2026-29643","datePublished":"2026-04-20T00:00:00.000Z","dateReserved":"2026-03-04T00:00:00.000Z","dateUpdated":"2026-04-20T21:18:39.405Z","state":"PUBLISHED"},"dataType":"CVE_RECORD","dataVersion":"5.2"},"nvd":{"publishedDate":"2026-04-20 22:16:23","lastModifiedDate":"2026-04-20 22:16:23","problem_types":["n/a"],"metrics":[],"configurations":[]},"legacy_mitre":{"record":{"CveYear":"2026","CveId":"29643","Ordinal":"1","Title":"CVE-2026-29643","CVE":"CVE-2026-29643","Year":"2026"},"notes":[{"CveYear":"2026","CveId":"29643","Ordinal":"1","NoteData":"XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.","Type":"Description","Title":"CVE-2026-29643"}]}}}