{"api_version":"1","generated_at":"2026-05-27T19:46:44+00:00","cve":"CVE-2026-45894","urls":{"html":"https://cve.report/CVE-2026-45894","api":"https://cve.report/api/cve/CVE-2026-45894.json","docs":"https://cve.report/api","cve_org":"https://www.cve.org/CVERecord?id=CVE-2026-45894","nvd":"https://nvd.nist.gov/vuln/detail/CVE-2026-45894"},"summary":{"title":"iommu/vt-d: Clear Present bit before tearing down PASID entry","description":"In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down PASID entry\n\nThe Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64\nbytes). When tearing down an entry, the current implementation zeros the\nentire 64-byte structure immediately using multiple 64-bit writes.\n\nSince the IOMMU hardware may fetch these 64 bytes using multiple\ninternal transactions (e.g., four 128-bit bursts), updating or zeroing\nthe entire entry while it is active (P=1) risks a \"torn\" read. If a\nhardware fetch occurs simultaneously with the CPU zeroing the entry, the\nhardware could observe an inconsistent state, leading to unpredictable\nbehavior or spurious faults.\n\nFollow the \"Guidance to Software for Invalidations\" in the VT-d spec\n(Section 6.5.3.3) by implementing the recommended ownership handshake:\n\n1. Clear only the 'Present' (P) bit of the PASID entry.\n2. Use a dma_wmb() to ensure the cleared bit is visible to hardware\n   before proceeding.\n3. Execute the required invalidation sequence (PASID cache, IOTLB, and\n   Device-TLB flush) to ensure the hardware has released all cached\n   references.\n4. Only after the flushes are complete, zero out the remaining fields\n   of the PASID entry.\n\nAlso, add a dma_wmb() in pasid_set_present() to ensure that all other\nfields of the PASID entry are visible to the hardware before the Present\nbit is set.","state":"PUBLISHED","assigner":"Linux","published_at":"2026-05-27 14:17:03","updated_at":"2026-05-27 14:48:31"},"problem_types":[],"metrics":[],"references":[{"url":"https://git.kernel.org/stable/c/821807c167b7b48a41b95b6607c6b9f97600f7d9","name":"https://git.kernel.org/stable/c/821807c167b7b48a41b95b6607c6b9f97600f7d9","refsource":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://git.kernel.org/stable/c/a84d30e8d2bacd21782a6481158b7c9c552f4868","name":"https://git.kernel.org/stable/c/a84d30e8d2bacd21782a6481158b7c9c552f4868","refsource":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://git.kernel.org/stable/c/75ed00055c059dedc47b5daaaa2f8a7a019138ff","name":"https://git.kernel.org/stable/c/75ed00055c059dedc47b5daaaa2f8a7a019138ff","refsource":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://git.kernel.org/stable/c/949d71666e9dd19f21e7b4b53a88cd2c5b902858","name":"https://git.kernel.org/stable/c/949d71666e9dd19f21e7b4b53a88cd2c5b902858","refsource":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","tags":[],"title":"","mime":"","httpstatus":"","archivestatus":"0"},{"url":"https://www.cve.org/CVERecord?id=CVE-2026-45894","name":"CVE Program record","refsource":"CVE.ORG","tags":["canonical"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2026-45894","name":"NVD vulnerability detail","refsource":"NVD","tags":["canonical","analysis"]}],"affected":[{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 a84d30e8d2bacd21782a6481158b7c9c552f4868 git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 821807c167b7b48a41b95b6607c6b9f97600f7d9 git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 949d71666e9dd19f21e7b4b53a88cd2c5b902858 git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15 75ed00055c059dedc47b5daaaa2f8a7a019138ff git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 5.0","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 5.0 semver","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 6.12.75 6.12.* semver","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 6.18.14 6.18.* semver","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 6.19.4 6.19.* semver","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 7.0 * original_commit_for_fix","platforms":[]}],"timeline":[],"solutions":[],"workarounds":[],"exploits":[],"credits":[],"nvd_cpes":[],"vendor_comments":[],"enrichments":{"kev":null,"epss":null,"legacy_qids":[]},"source_records":{"cve_program":{"containers":{"cna":{"affected":[{"defaultStatus":"unaffected","product":"Linux","programFiles":["drivers/iommu/intel/pasid.c","drivers/iommu/intel/pasid.h"],"repo":"https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git","vendor":"Linux","versions":[{"lessThan":"a84d30e8d2bacd21782a6481158b7c9c552f4868","status":"affected","version":"0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15","versionType":"git"},{"lessThan":"821807c167b7b48a41b95b6607c6b9f97600f7d9","status":"affected","version":"0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15","versionType":"git"},{"lessThan":"949d71666e9dd19f21e7b4b53a88cd2c5b902858","status":"affected","version":"0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15","versionType":"git"},{"lessThan":"75ed00055c059dedc47b5daaaa2f8a7a019138ff","status":"affected","version":"0bbeb01a4fafbf8422e5c8882d461d6ac4f71e15","versionType":"git"}]},{"defaultStatus":"affected","product":"Linux","programFiles":["drivers/iommu/intel/pasid.c","drivers/iommu/intel/pasid.h"],"repo":"https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git","vendor":"Linux","versions":[{"status":"affected","version":"5.0"},{"lessThan":"5.0","status":"unaffected","version":"0","versionType":"semver"},{"lessThanOrEqual":"6.12.*","status":"unaffected","version":"6.12.75","versionType":"semver"},{"lessThanOrEqual":"6.18.*","status":"unaffected","version":"6.18.14","versionType":"semver"},{"lessThanOrEqual":"6.19.*","status":"unaffected","version":"6.19.4","versionType":"semver"},{"lessThanOrEqual":"*","status":"unaffected","version":"7.0","versionType":"original_commit_for_fix"}]}],"cpeApplicability":[{"nodes":[{"cpeMatch":[{"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionEndExcluding":"6.12.75","versionStartIncluding":"5.0","vulnerable":true},{"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionEndExcluding":"6.18.14","versionStartIncluding":"5.0","vulnerable":true},{"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionEndExcluding":"6.19.4","versionStartIncluding":"5.0","vulnerable":true},{"criteria":"cpe:2.3:o:linux:linux_kernel:*:*:*:*:*:*:*:*","versionEndExcluding":"7.0","versionStartIncluding":"5.0","vulnerable":true}],"negate":false,"operator":"OR"}]}],"descriptions":[{"lang":"en","value":"In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down PASID entry\n\nThe Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64\nbytes). When tearing down an entry, the current implementation zeros the\nentire 64-byte structure immediately using multiple 64-bit writes.\n\nSince the IOMMU hardware may fetch these 64 bytes using multiple\ninternal transactions (e.g., four 128-bit bursts), updating or zeroing\nthe entire entry while it is active (P=1) risks a \"torn\" read. If a\nhardware fetch occurs simultaneously with the CPU zeroing the entry, the\nhardware could observe an inconsistent state, leading to unpredictable\nbehavior or spurious faults.\n\nFollow the \"Guidance to Software for Invalidations\" in the VT-d spec\n(Section 6.5.3.3) by implementing the recommended ownership handshake:\n\n1. Clear only the 'Present' (P) bit of the PASID entry.\n2. Use a dma_wmb() to ensure the cleared bit is visible to hardware\n   before proceeding.\n3. Execute the required invalidation sequence (PASID cache, IOTLB, and\n   Device-TLB flush) to ensure the hardware has released all cached\n   references.\n4. Only after the flushes are complete, zero out the remaining fields\n   of the PASID entry.\n\nAlso, add a dma_wmb() in pasid_set_present() to ensure that all other\nfields of the PASID entry are visible to the hardware before the Present\nbit is set."}],"providerMetadata":{"dateUpdated":"2026-05-27T12:17:04.866Z","orgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","shortName":"Linux"},"references":[{"url":"https://git.kernel.org/stable/c/a84d30e8d2bacd21782a6481158b7c9c552f4868"},{"url":"https://git.kernel.org/stable/c/821807c167b7b48a41b95b6607c6b9f97600f7d9"},{"url":"https://git.kernel.org/stable/c/949d71666e9dd19f21e7b4b53a88cd2c5b902858"},{"url":"https://git.kernel.org/stable/c/75ed00055c059dedc47b5daaaa2f8a7a019138ff"}],"title":"iommu/vt-d: Clear Present bit before tearing down PASID entry","x_generator":{"engine":"bippy-1.2.0"}}},"cveMetadata":{"assignerOrgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","assignerShortName":"Linux","cveId":"CVE-2026-45894","datePublished":"2026-05-27T12:17:04.866Z","dateReserved":"2026-05-13T15:03:33.083Z","dateUpdated":"2026-05-27T12:17:04.866Z","state":"PUBLISHED"},"dataType":"CVE_RECORD","dataVersion":"5.2"},"nvd":{"publishedDate":"2026-05-27 14:17:03","lastModifiedDate":"2026-05-27 14:48:31","problem_types":[],"metrics":[],"configurations":[]},"legacy_mitre":{"record":{"CveYear":"2026","CveId":"45894","Ordinal":"1","Title":"iommu/vt-d: Clear Present bit before tearing down PASID entry","CVE":"CVE-2026-45894","Year":"2026"},"notes":[{"CveYear":"2026","CveId":"45894","Ordinal":"1","NoteData":"In the Linux kernel, the following vulnerability has been resolved:\n\niommu/vt-d: Clear Present bit before tearing down PASID entry\n\nThe Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64\nbytes). When tearing down an entry, the current implementation zeros the\nentire 64-byte structure immediately using multiple 64-bit writes.\n\nSince the IOMMU hardware may fetch these 64 bytes using multiple\ninternal transactions (e.g., four 128-bit bursts), updating or zeroing\nthe entire entry while it is active (P=1) risks a \"torn\" read. If a\nhardware fetch occurs simultaneously with the CPU zeroing the entry, the\nhardware could observe an inconsistent state, leading to unpredictable\nbehavior or spurious faults.\n\nFollow the \"Guidance to Software for Invalidations\" in the VT-d spec\n(Section 6.5.3.3) by implementing the recommended ownership handshake:\n\n1. Clear only the 'Present' (P) bit of the PASID entry.\n2. Use a dma_wmb() to ensure the cleared bit is visible to hardware\n   before proceeding.\n3. Execute the required invalidation sequence (PASID cache, IOTLB, and\n   Device-TLB flush) to ensure the hardware has released all cached\n   references.\n4. Only after the flushes are complete, zero out the remaining fields\n   of the PASID entry.\n\nAlso, add a dma_wmb() in pasid_set_present() to ensure that all other\nfields of the PASID entry are visible to the hardware before the Present\nbit is set.","Type":"Description","Title":"iommu/vt-d: Clear Present bit before tearing down PASID entry"}]}}}