{"api_version":"1","generated_at":"2026-08-24T20:54:52+00:00","cve":"CVE-2026-50719","urls":{"html":"https://cve.report/CVE-2026-50719","api":"https://cve.report/api/cve/CVE-2026-50719.json","docs":"https://cve.report/api","cve_org":"https://www.cve.org/CVERecord?id=CVE-2026-50719","nvd":"https://nvd.nist.gov/vuln/detail/CVE-2026-50719"},"summary":{"title":"CVE-2026-50719","description":"The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. 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The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. This has been hardware-validated on a secureboot-enabled T41 device; ROM analysis confirms closely related behavior on T32, T40, and A1.","Type":"Description","Title":"CVE-2026-50719"}]}}}