{"api_version":"1","generated_at":"2026-11-10T17:39:24+00:00","cve":"CVE-2026-99099","urls":{"html":"https://cve.report/CVE-2026-99099","api":"https://cve.report/api/cve/CVE-2026-99099.json","docs":"https://cve.report/api","cve_org":"https://www.cve.org/CVERecord?id=CVE-2026-99099","nvd":"https://nvd.nist.gov/vuln/detail/CVE-2026-99099"},"summary":{"title":"x86/CPU/AMD: Fix AMD TLBI Erratum #1718","description":"In the Linux kernel, the following vulnerability has been resolved:\n\nx86/CPU/AMD: Fix AMD TLBI Erratum #1718\n\nThe processor may fail to invalidate a TLB entry while executing an\nINVLPGB/TLBSYNC instruction pair.\n\nDetect the erratum and apply a software workaround when a microcode fix\nis not present.","state":"PUBLISHED","assigner":"Linux","published_at":"2026-10-26 15:16:48","updated_at":"2026-10-31 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Program record","refsource":"CVE.ORG","tags":["canonical"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2026-99099","name":"NVD vulnerability detail","refsource":"NVD","tags":["canonical","analysis"]}],"affected":[{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 82378c6c2f435dba66145609de16bf44a9de6303 e3e6779f77ab6f0a1aa80e24868d2d89f31053fe git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 82378c6c2f435dba66145609de16bf44a9de6303 098d80b04d0fe02889c332d061db968f070b83a6 git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 82378c6c2f435dba66145609de16bf44a9de6303 87db7795cbaaf636ae22ae031f4906db7bb77803 git","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"affected 6.15","platforms":[]},{"source":"CNA","vendor":"Linux","product":"Linux","version":"unaffected 6.15 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the Linux kernel, the following vulnerability has been resolved:\n\nx86/CPU/AMD: Fix AMD TLBI Erratum #1718\n\nThe processor may fail to invalidate a TLB entry while executing an\nINVLPGB/TLBSYNC instruction pair.\n\nDetect the erratum and apply a software workaround when a microcode fix\nis not present."}],"metrics":[{"cvssV3_1":{"baseScore":7.8,"baseSeverity":"HIGH","vectorString":"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H","version":"3.1"},"scenarios":[{"lang":"en","value":"AV:L - SYSCALL_DEFINE2(munmap)→__vm_munmap→do_vmi_munmap→do_vmi_align_munmap→vms_complete_munmap_vmas→vms_clear_ptes→unmap_region, which runs unmap_vmas then tlb_finish_mmu→tlb_flush_mmu→tlb_flush→flush_tlb_mm_range→broadcast_tlb_flush→patched __tlbsync; no wire protocol carries the trigger.\nAC:L - An attacker can keep one mm active on four CPUs and repeat munmap until consider_global_asid() assigns a broadcast ASID, prime the target TLB entry, and repeatedly exercise the faulty pair while grooming reuse. CONFIG_BROADCAST_TLB_FLUSH is default on AMD64, and all timing/setup is controlled by the attacker's threads.\nPR:L - SYSCALL_DEFINE2(munmap) reaches the path for ordinary anonymous mappings; do_vmi_munmap() only validates the range, and __vm_munmap() only locks current->mm. No capability, authentication, device permission, or privileged namespace operation is required.\nUI:N - The attacker's own threads create and touch a mapping, call munmap(), and access the stale virtual address after reuse. No victim must mount media, open a file, or perform another action.\nS:U - The failed __tlbsync() leaves a stale host CPU translation and compromises pages managed by the same host kernel. This is ordinary local kernel compromise, not a guest-to-host escape or an IOMMU-boundary bypass.\nC:H - zap_present_folio_ptes() clears the PTE and queues its folio, but tlb_finish_mmu() trusts the faulty __tlbsync() before tlb_batch_pages_flush() recycles it through free_pages_and_swap_cache(). The cached user translation can then read the recycled page, including kernel or other-process data.\nI:H - The same stale writable translation bypasses the cleared page table after free_pages_and_swap_cache() recycles the folio. Grooming that page into kernel objects or page tables provides a kernel-memory write primitive capable of control-flow hijacking.\nA:H - Writes through the stale translation can corrupt a recycled page table or kernel object and cause an oops, panic, or hang. The earlier tlbi=ipi mitigation commit also identifies this INVLPGB/TLBSYNC defect as a cause of observed userspace crashes."}]}],"providerMetadata":{"dateUpdated":"2026-10-31T12:42:48.094Z","orgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","shortName":"Linux"},"references":[{"url":"https://git.kernel.org/stable/c/e3e6779f77ab6f0a1aa80e24868d2d89f31053fe"},{"url":"https://git.kernel.org/stable/c/098d80b04d0fe02889c332d061db968f070b83a6"},{"url":"https://git.kernel.org/stable/c/87db7795cbaaf636ae22ae031f4906db7bb77803"}],"title":"x86/CPU/AMD: Fix AMD TLBI Erratum #1718","x_generator":{"engine":"bippy-1.2.0"}}},"cveMetadata":{"assignerOrgId":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","assignerShortName":"Linux","cveId":"CVE-2026-99099","datePublished":"2026-10-26T14:52:04.997Z","dateReserved":"2026-09-25T10:25:14.391Z","dateUpdated":"2026-10-31T12:42:48.094Z","state":"PUBLISHED"},"dataType":"CVE_RECORD","dataVersion":"5.2"},"nvd":{"publishedDate":"2026-10-26 15:16:48","lastModifiedDate":"2026-10-31 13:17:55","problem_types":[],"metrics":{"cvssMetricV31":[{"source":"416baaa9-dc9f-4396-8d5f-8c081fb06d67","type":"Secondary","cvssData":{"version":"3.1","vectorString":"CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H","baseScore":7.8,"baseSeverity":"HIGH","attackVector":"LOCAL","attackComplexity":"LOW","privilegesRequired":"LOW","userInteraction":"NONE","scope":"UNCHANGED","confidentialityImpact":"HIGH","integrityImpact":"HIGH","availabilityImpact":"HIGH"},"exploitabilityScore":1.8,"impactScore":5.9}]},"configurations":[]},"legacy_mitre":{"record":{"CveYear":"2026","CveId":"99099","Ordinal":"1","Title":"x86/CPU/AMD: Fix AMD TLBI Erratum #1718","CVE":"CVE-2026-99099","Year":"2026"},"notes":[{"CveYear":"2026","CveId":"99099","Ordinal":"1","NoteData":"In the Linux kernel, the following vulnerability has been resolved:\n\nx86/CPU/AMD: Fix AMD TLBI Erratum #1718\n\nThe processor may fail to invalidate a TLB entry while executing an\nINVLPGB/TLBSYNC instruction pair.\n\nDetect the erratum and apply a software workaround when a microcode fix\nis not present.","Type":"Description","Title":"x86/CPU/AMD: Fix AMD TLBI Erratum #1718"}]}}}